1. Field of the Invention
The present invention relates generally to solid state digital logic circuits and particularly to bipolar, emitter coupled logic (ECL) circuits. More particularly, the present invention relates to detection circuits for testing the operation and integrity of one or more circuit elements.
2. Background and Related Art
Digital logic circuits in current generation computers are frequently implemented as VLSI circuits. Bipolar emitter coupled logic (ECL) circuits predominate and are found in, for example, the IBM ES/9000 series of large computers.
Logic circuits have traditionally been implemented as current switch emitter follower (CSEF) circuits. More recently, differential current switch logic circuits (DCS) have been proposed to increase circuit speed without an accompanying increase in power. U.S. Pat. No. 4,760,289 to Eichelberger et al. (commonly assigned) for a "Two Level Differential Cascode Current Switch Masterslice" is an example of such a circuit and is incorporated by reference. The DCS circuit described in Eichelberger et al. improves switching speed by up to twenty percent without an increase in power.
Logic circuits, whether CSEF or DCS, are subject to failure due to VLSI defects. Most such defects lead to catastrophic circuit failure which can be effectively modelled by stuck faults. These stuck faults can be tested with test vectors which propagate the fault to observable points.
A second class of VLSI defects leads to reduced signal levels at circuit output nodes. The reduced signal may be interpreted as either a high value or low value by the circuits loading it. In the worst case, some loads may interpret the signal as high while others interpret it as low. This class of defects is considered untestable and results in reduced product quality and may affect product reliability.
A DCS signal is represented by the difference between two complementary signals. A VLSI defect, such as a global short or open, may cause one of the two outputs to fall to an intermediate level while the other output is fully functional. The resultant reduced difference signal or low margin signal, may be intermittent and untestable.
Prior art DCS systems have addressed this problem by adding a test biasing scheme to the DCS circuit. The test biasing circuitry pulls current from nodes internal to the DCS circuit. This creates problems, however, because the biasing circuitry even when off slows the circuit due to the criticality of these nodes to circuit performance. Inclusion of biasing circuitry also complicates the DC design of the circuit as the test bias current depends upon power level, circuit type and output dotting. If the outputs are shifted with a shift resistor the test bias circuit may not be designable due to potential saturation problems.